Error correcting digital coding and decoding apparatus



Oct. 6, 1970 N. ZIERLER ET AL ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS Filed June 15. 1967 19 Sheets-Sheet 1 READ-WRITE MEMORY g I3 (5 ill DATA A DATA SOURCE- BUFFER gkgw SOURCE- SINK I I suxu ,9 FINITE FIELD ARITHMETRIC UNIT FIG. I

INVENTORS NEAL ZIERLER BY JOHN TERZIAN zxizgmsvs OEI, a, 17 I N. ZIERLEE HAL 3,

ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS Filed June 15. 196'? 19 Sheets-Sheet 2 I F M SINGLE m CONTROL 1 ADDRESS Address Bus M MA MEMORY DIGITAL I is] I COMPUTER I I I I I READ-WRITE I MEMORY MB ii w I F' SIIIPBUS M TEEnTcTI\ PC MEANS i Loud MAJOR SWR Adclmss 2h STATE I L GENERATOR -Deposw I L A0 I CONTROL BREAK A AND OOMTMOI. AC M W TIMING no) In M O I III Timin A 53$ gu s 315 mi figwml WW I I I #1:" "L155 49 I I0 Bus; 11 m" .:I..m i

Timing l8 Bus AAFL OO4P IBRO--\ AC OuIpuI Bus AC Inpm Bus mvm I i 25 FFM ,,8 8 Maawg CONTROL M I CIRCUITS B-AC MB I B-AC MB I? I W I Fm R1 R2 C SEIEEIJIIMO EA GATES L Address Bus K15 III;

7 INYENNJRS zgiigg g NEAL ZIERLER UNIT JOHN TERZIAN N. ZIERLER ETAL I 3,533,067

ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS Oct. 6, 1970 Filed June 15; 1967 19 Sheets-Sheet 3 s EEG 5301 Q 25% m NIUIM wSowxw w m MEE E mo .zT SE28 105E M m EBEEZ E0 oil 2569K NJ I mm @5950 m 39 6528 N19 024 mok mwzww 6528 02:2; T 5.45 @033 viwmm 0%. E9 I I A IN 8 3 8 C E5080 5 8 E NP I I A 5880 m 295352 awpzwzwnq I E .92 m @E Emwmo I I I I I I o mm-wmno m2 92 I ZiTOANEYS Oct. 6, 1970 N Z|ERLER E'I'AL 3,533,067

ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS Filed June 15. 1967 19 Sheets-Sheet 4.

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ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS V Filed June 15, 196? 19 Sheets Sheet 5 SIGNIFICANCE' FOR GROUP I Fl 8 f CML G CMR F g 1 CLA CLL Rotation Count ew sfilffuuef Ol23456789l0|l v 5H CL" HLT SMA

SZA Reverse Skip Sensing SNL SIGNIFICANCE FOR GROUP JI 0 1 ,usec ?-,usec I 5psec 3, 75psec tort of Fetch Start of "1m Fetch Cycle flgfi f ii y Clock Output 1 n FL L Memory Start i Instruction ini MB not m POUSE 1 Flip-Flop 0 Y I TipsecT-iysecj Composit IOP Pulse I I Generator j IOPI IOPZ Output Puise if Pulse if MB 11 (1) MB10(1) Restart Sync. 1 Flip-Flop 0 I Genfirated t1 y first CIOCIt output wen esa s IO Restart r r ync Fl INVENTORS NEAL Z-IERLER wr mtee 0a. 6, 1970 N, ZERLER E-TAL 3,533,067

ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS Filed June 15. 1967 19 Sheets-Sheet 6 T1T1A T2 T1 T2 Add available 1 I fess MA not available I L Transfer Direction g'gJ I l I Break Request, 6004 no {3332:} I l L Brk Sync Flip-Flop f, I

Data Address MA Pulse FIG. l0 *5 Break Signal Dam in MB available not available 1 MA available I fess not available Transfer Direction 3L] Break Request,6004 :233:21: I l Brk Sync Flip-Flop :3 fi' Data Address MA Pulse HG. it MP 5 1 Break Signal Increment Request request "5--- to MB no request Memory Strobe Transfers the Content of the Selected U Memory Location into the MB Increment MB Content of MB into the Selected Memory Location Write Signal Writes the l INVENTORS NEAL ZIERLER BY JOHN TERZlAN N. ZIERLER ET L 3,533,067

ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS l9 Sheets-Sheet 7 Oct. 6, 1970 Filed Jugs 15. 1967 2 01 s F m f R m. m 2 50 Q4 0 864 :64 664 mam A g mmm 4 E 4 inn. 5 2T AW a F m m 0 m w 0 K m 0 m d "5 6 o F 189 1084 m 040 :m an :O 04 :4 m 3 3 4 304404 moo4+o ww 4 44 8% A m. c 4 4 M m4 m4 4.4 m4 9T n T s ,w A m D Z 584 V a O m G mm mm m 4 7 mm A E h; m+o A Q43 4 A 38 @2442 F35 2 4 @094 N094 85o Q24 N E. S 4 mm 4 EN 4 t m 5 04 -m mam 3234 v.35

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Oct. 6, 1970 N. ZIERLER ETAL ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS l9 Sheets-Sheet 9 m 64 004 m R ME mm 4 WRZ y Em 2T, LN mm NJ E mmz mmz 4 Es o Filed June 15. 196? Oct. 6, 1970 N. ZIERLER El' AL 19 s eets-sheet 10 Filed June 15. 1967 mam 89 102m S 54 RE 84 $4 m T N N A W mm 4 .8 mm 4 mm m fi LN @W N J Y B :3 m2 oE NE: 7 h 084 m9 F4 4 5 mm 9 8. H p H H v m u m m u m o z m o m EE 9 2m RE 35 n O a u O a v O 7 Cm 9m 2m Em 0 N. ZIERLER ETAL ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS Filed June 15. 1967 19 Sheets-Sheet l2 I M I F m 0 m m 0 m iiv Ewm 95m 4 O a O 32 4mm 0mm N84 8. m s 2 I TERZIAN ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS Oct. 6, 1970 N. ZIERLER ETAL l9 Sheets-Sheet 15 Filed June 15. 1 967 9 m 32:0 04 5 2 304 5304 2.54 664 o Iii mam m U T v Y W HR T my 4 mm. a my 4 y 4 w v A so dd 5 Q4 50 NJ I I 22 6 Y \IEQEQ. OQD B 87035 X0333 5 mm. 5 m9 .5 mm. 5 8 F G 9% {ll Iv k? m o m m u a m u m m3 :6 III I :0 a o d o a O Y F v r OIL T O 5o 2 7 0 9 oflo o N. ZIERLER ETAL 3,533,067

ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS 19 Sheets-Sheet M.

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EE A v ZT ERROR CORRECTING DIGITAL CODING AND DECODING APPARATUS Filed June 15. 1967 Oct. 6, 1970 N. ZVIIERLER ETAL 19 Sheets-Sheet 17 iNVENTORS NEAL ZIERLER BY JOHN TERZIAN TTORNEYS Oct. 6,1970 N. ZIERLER ETAL ,5 ,06

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United States Patent US. Cl. 340-4461 Claims ABSTRACT OF THE DISCLOSURE Apparatus for coding and decoding m-bit digital signals in an error correcting code characterized by blocks of mbit signals of fixed length including signals representing message symbols and signals representing check symbols, the latter being computed so that a predetermined number of symbol errors can be detected and corrected by evaluating functions of the contents of the block. The apparatus comprises a memory, a finite field arithmetic unit, and sequencing means for exchanging information between the memory and the arithmetic unit to perform rapid calculations, such as the evaluation of polynomials and matrix reductions, in finite field arithmetic. The full specification should be consulted for an understanding of the invention.

Our invention relates to digital data processing, and particularly to novel apparatus for coding and decoding digital information in an error correcting code.

Digital communication channels, which may include wire links, radio links, or both, are subject to error rates that generally increase with the bit rate of information transfer and are directly affected by noise in the channel. Radio transmission channels are associated with particularly high error rates caused by noise, fading and interference. Various expedients have been devised for using channels of this kind. All involve a compromise between channel bandwidth, cost and complexity of transmitting and receiving equipment, and the useful bit rate of information transfer.

In many instances, it is necessary to use a communication channel of limited bandwidth and quality, and economics dictates definite upper limits on the cost and complexity of the transmitting and receiving equipment. Under those circumstances, it is necessary to introduce sufiicient redundancy into the data transmitted so that the existing error rate can be tolerated.

One approach is to simply repeat the transmitted information until it can be assumed to have been received. A more efiicient method, effective when some errors are permissible, is to employ an error detecting code, such as those codes in which parity bits are included. Using such a code, a class of errors can be detected at the receiving end of the channel, making it possible to request re-transmission of information in which an error has been detected. In principle, a much more powerful approach is to transmit the information in an error-correcting code. Many such codes have been developed, and they share the property that redundant information is incorporated in the transmitted data in such a way that the data can be reconstituted if no more than a predetermined number of randomly distributed errors have occurred. Some error correcting codes are impractical, because they involve too high a degree of redundancy for the number of errors that can be corrected, thereby defeating the purpose of a high speed communication channel. Prior to our invention, even those codes involving an acceptable degree of redundancy have found little use, because either they are relatively ineffective or the apparatus required to decode 3,533,067 Patented Get. 6, 1970 the information and correct any errors that may be found has been too complex and costly. The object of our invention is to facilitate the coding and decoding of information in an error-correcting code, thereby making it practical to use the code in digital communication channels.

The codes usable with the apparatus of our invention are of a class in which code blocks are employed. Each code block includes a group of m-bit symbols each representing a data character, and a group of m-bit check symbols computed from the data symbols, the total number of symbols in each block being a constant. If data is so encoded, and certain additional constraints to be described below are observed, so long as there remains a number of correct symbols in the block equal to the number of data symbols plus at least half of the check symbols, then the other symbols can be corrected even though each bit in each of them is in error. Moreover, if there are additional symbols in error, it is possible to discover that there are too many errors to correct and take appropriate action. The two functions which the apparatus of our invention is especially adapted to perform are the coding of data into error correcting code blocks and the performance of the decoding process on data so encoded. Following the decoding of a block of signals, the apparatus will either supply the decoded data in corrected form to a data sink, or provide an indication that an uncorrectable number or errors have occurred.

Briefly, the apparatus of our invention comprises a random access memory, a finite field arithmetic unit, and sequencing means for exchanging information between the memory and the arithmetic unit. A buffer is provided for exchanging information between this apparatus and a communications link, and means are provided for supplying decoded information to a data sink.

The finite field arithmetic unit includes a set of registers, a finite field adder, and a finite field multiplier. The sequencing means comprises apparatus for storing a block of encoded data in the memory, and thereafter sequentially making a predetermined set of interconnections between the memory and the various components of the arithmetic unit. During coding, the apparatus computes the check symbols needed to provide a complete code block. During decoding, the apparatus progressively detects any errors that are present in the encoded data, provides an indication if there are too many to correct, computes the correct data when a suitably limited number of errors have been detected, and supplies the corrected and decoded data to the data sink.

The apparatus of our invention, and its mode of operation, will best be understood in the light of the following detailed description, together with the accompanying drawings, of a preferred embodiment thereof.

In the drawings,

FIG. 1 is a block diagram of coding and decoding apparatus in accordance with our invention connected as a station in a communication link;

FIG. 2 is a block diagram showing portions of the apparatus of FIG. 1 in somewhat more detail;

FIG. 3 is a block diagram of a portion of a conventional digital computer used to form a part of the apparatus of FIGS. 1 and 2 in accordance with the particular embodiment of our invention to be described;

FIG. 4 is a timing diagram showing basic timing pulses occurring in the operation of the apparatus of FIGS. 1 and 2 in the embodiment incorporating the computer of FIG. 3;

FIG. 5 is a schematic wiring diagram illustrating certain modifications of the computer of FIG. 3 made in order to adapt it for use in the coding and decoding apparatus of our invention; 

